The present invention relates to the art of data handling. It finds particular application in conjunction with DMA memory address generators for handling large blocks of image data for medical and diagnostic scanners and will be described with particular reference thereto. However, it is to be appreciated that the invention is also applicable to DMA controllers and address generators for other purposes, such as refreshing displayed images, writing data into DRAM, VRAM or other memories, or writing data directly from DRAM, VRAM, or other memories, and the like.
Heretofore, a processor generated an address for each element of data which was moved from one location to another, e.g., each element of data stored in or retrieved from a memory. When moving large blocks of data, such as images, generating the many addresses consumed a large portion of the processor's time. To free the processor for other tasks, direct memory access (DMA) controllers were used to generate the series of addresses. This enabled the data to be stored, retrieved, or otherwise moved without the intervention of the microprocessor or other central processing unit. This freed the processor to perform other functions expediting the data transfer process.
Heretofore, DMA controller devices have had both a data bus for receiving instructions and an address bus for outputting the series of addresses. In a 32 bit system, for example, the data and address buses each had 32 parallel leads or pin sets for interconnection with associated hardware. The DMA controller included a logic or processor portion, a starting address register, and a transfer size or ending address register connected with the data bus. The data bus carried an identification or enable signal which enabled the DMA to start generating the sequence of addresses, the start address, and an indication of the data block size or end address. The starting address and the data block size or end address were loaded in the corresponding registers. A series of counters were loaded with start address and the data block size or end address. The counters were clocked in synchronization with an external event indicative of the data movement to generate an address for each moved data element. With each cycle, the counters were incremented such that each clocking generated the next address.
One drawback of the prior art DMA systems is that they became hardware cumbersome and expensive with larger numbers of bits. A first or data bus was required to pass the DMA starting address and transfer length and a second or address bus was required to output a sequential DMA addresses. The DMA control circuit interfaced with a large number of signal lines in the two complete buses, requiring large printed circuit board surface area dedicated to signal routing. This increased printed circuit board complexity. Further, the controller itself had to be large to accommodate the large number of inputs and outputs.
Another problem with the prior art is that the multiple counters are expensive in logic resources, which expense increases with increasing address ranges that require more complex counter designs.
The present invention contemplates a new and improved DMA architecture which overcomes the above-referenced problems and others.